1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the time-division multiplexing of processing circuitry within an integrated circuit.
2. Description of the Prior Art
It is known to provide integrated circuits with multiple instances of the same processing circuitry formed on the integrated circuit and operated in parallel to increase data processing throughput. An example of such integrated circuits are those employing symmetric multiprocessor architectures in which multiple processing cores are formed on a single integrated circuit and controlled by a snoop control unit to ensure memory coherence between the multiple processor cores. A problem with these increasingly complex designs is that the large gate count makes it difficult to simulate the design with a field programmable gate array (FPGA) typically used during early development and to allow software to be developed prior to the integrated circuit itself being manufactured. The size of FPGA integrated circuits has generally not kept pace with the increase in gate count of integrated circuits, such as those employing SMP techniques. A consequence of this is that a single SMP integrated circuit may need to be represented by multiple FPGA integrated circuits. This has significant price and performance disadvantages. The FPGA integrated circuits are themselves expensive and a requirement for more of these to be used to provide the model of the eventual production integrated circuit is a disadvantage. Furthermore, the communication necessary between FPGA integrated circuits slows the overall operation of the model as such off-chip communications are typically slow compared to on-chip communications.